A MOS field effect transistor (MOSFET) may offer numerous advantages such as a high input impedance over a bipolar transistor, a large power gain and a simple structure for a gate driving circuit since it is a unipolar device, and does not generate a time delay due to the accumulation or the re-combination of a minority carrier. Accordingly, MOSFETs have applicability as a switching mode power supply, a lamp ballast and a motor driving circuit.
A power MOSFET, a double diffused MOSFET structure (DMOSFET) using planar diffusion technique has been widely used. It may be important for the DMOS transistors to apply to a power device capable of processing high voltage. An advantage of DMOSFETs is current handling capacity per unit area or on-resistance per unit area. Since voltage ratio may be fixed, the on-resistance per unit area can be reduced as the cell area of the MOS device is reduced.
In the field of the power transistor, the cell pitch thereof may be defined by a coupled width of poly crystalline silicon (polysilicon) and a contact region forming gate and source electrodes, respectively.
The width of the polysilicon region of a DMOS power transistor can be accomplished by reducing a junction depth of a p-type well. The minimum junction depth may be defined by a required breakdown voltage.
An LDMOS device may be suitable for applying to a VLSI process due to its simple structure. However, such LDMOS devices exhibit poor characteristics as compared to a vertical DMOS (VDMOS). With the development of reduced surface field (RESURF) LDMOS devices, the LDMOS devices have obtained excellent on-resistance (Rsp). However, the structure of the RESURF device may be applied only to source-grounded devices and may be very complicated.
DMOS transistors have been used as a discontinuous power transistor or components in a monolithic integrated circuit. In order to prepare a self-aligned channel region along with a gate, a channel body region may be formed by the implantation of a dopant (p-type or n-type impurity) through apertures in a mask made of a gate forming material.
A source region may be formed by implanting a dopant through the apertures, the dopant having a conductivity opposite to the conductivity of the channel body region. The source may be self-aligned to both of the gate electrode and the channel body region to derive a relatively compact structure.
As illustrated in example in FIG. 1, an LDMOS semiconductor device may include STI-type device isolating layer 12 formed in an active region and a device isolating region of silicon substrate 11, which is defined as a device isolating region. N+ well region 13 may be formed in the surface of silicon substrate 11 at a predetermined depth. P+ body layer 14 may be formed in the surface of silicon substrate 11 formed with N+ well region 13. A plurality of source regions (N+) 15 may be formed in the surface of P+ body layer 14 at a predetermined interval. P+ body region 16 may be formed in P-body layer 14 between source regions (N+) 15. Gate electrode 18 may be formed by having a predetermined interval. Gate insulating layer 17 may be formed laterally to a side of source region (N+) 15. Drain region (N+) 19 may be formed in N-well region 13 laterally with respect to gate electrode 18.
Such an LDMOS device may utilize device isolating layer 12 as a filed plate in order to obtain high voltage by reducing field in an edge portion of gate electrode 18. However, such a structure may result in an increase in on-resistance due to an increase of the current path.